This disclosure relates to circuits for discerning the logic value stored in a memory bit cell or other storage element.
The logic value is discerned by whether rates of voltage discharge when commencing a memory read operation are characteristic of a conductive path of higher resistance or lower resistance through the bit line to a supply voltage. The bit line discharges more or less quickly than a reference bit line emulating a resistance value between higher and lower resistance values of the bit cell in its distinct logic states. The rates of discharge are compared by latching the sensing circuit into an output state that represents which of the bit line and the reference line was first to discharge to a threshold voltage. The disclosed techniques are applicable generally to memory and data storage applications characterized by a difference in bit line resistance through a memory element when in different logic states.
According to embodiments of the present disclosure, a precharged bit line can be viewed as a charged capacitance. When a bit cell is addressed for a read operation, the bit cell is coupled along the associated bit line to the power supply and to the sense amplifier. The sense amplifier input represents a load, discharging the bit line through the bit cell resistance coupled back to the power supply. The resistance path has a relatively higher or lower resistance in different logic states of the bit cell. The voltage on the bit line discharges more or less quickly depending on the bit cell logic state.
Typical sense amplifiers compare differences in voltage, for example on complementary bit lines. A sense amplifier latch is enabled at a short time after a read operation commences. If the sense amplifier is enabled after a very short time delay, the voltage divergence of complementary bit lines may be small. In a similar circuit arrangement, a sense amplifier may compare the voltages of a single bit line versus the voltage on a reference bit line (rather than comparing the voltages of complementary lines). Again, if the sense amplifier is enabled after a very short time delay, the divergence between the bit line voltage and the reference bit line voltage may be small.
If the divergence of the voltages being compared is less than the offset of the sense amplifier, the enabled sense amplifier may latch or commence to latch into a logic state that is not the same as the logic state of the bit cell whose logic state is supposed to be copied to the sense amplifier latch. In a situation wherein the bit cell and the sense amplifier each have a latch (such as cross-coupled inverters, for example), the sense amplifier latch and the bit cell latch oppose one another. The output data value from the sense amplifier latch may be erroneous, or the sense amplifier latch may force the bit cell latch to change state, in a so-called read disturb error. Conventionally, the sense amplifier enable signal needs to be delayed until the divergence of the bit line voltages (namely the difference between complementary bit line voltages or the difference between a bit line voltage and a reference voltage) exceeds the worst-case sense amplifier offset for all the bit cells in an addressed memory word. But it is desirable that the time delay be brief so that the memory cycle time for a read operation on the memory can be short and the memory can be clocked at a high frequency.
What is needed is a circuit and technique whereby a sense amplifier can be enabled shortly after the read operation commences, even as soon as a word line address signal becomes true. Advantageously, the sense amplifier should become latched early but dependably into a state representing the logic state of the bit cell being read out. An optimal sensing circuit will not rely on aspects that are potentially ambiguous for a time when the read operation begins, such as a comparison of voltages on a bit line BL and a reference line REFBL. In particular, a fast sensing circuit is needed that does not require voltage divergence exceeding an offset voltage of a comparator used as a sense amplifier when reading out the logic state of a bit cell that has been enabled for reading (e.g., addressed). Circuits and techniques are needed that read bit cell logic values dependably without unnecessary delay.